Layout Generator for Routing and Designing an LSI

ABSTRACT

According to the present invention an automated layout generator is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.

RELATED APPLICATION

This application is a division of U.S. Ser. No. 10/983,819 filed Nov. 8,2004, entitled Automatic Method for Routing and Designing an LSI,claiming priority of EPO 03104166.8

BACKGROUND OF THE INVENTION

The present invention relates in general to an automated layoutgenerator utilized for routing and designing an LSI. More particularly,the present invention relates to a layout generator which considers anduses interdependencies between routing and designing of the instances ofbooks to be routed. Specifically, the present invention employs arouting which provides design parameters for the layout of the instancesto optimize the density of the circuits and wiring on the chip overall.

Besides, the present invention relates to a wiring tool for routing theinstances of the books of an LSI and to a layout generator for creatingthe layout of the instances of the books of an LSI, which are especiallydesigned to carry out an automated method for routing and designing anLSI according to the present invention.

DESCRIPTION OF THE RELATED ART

The growing complexity of integrated circuits is limited by the densityof local wiring but not by the density of silicon used for circuits. Ifthe area used for circuits exceeds about 60% of the chip area it becomesvery difficult if not impossible to connect these circuits. So anyincrease of the wiring density will increase the density of the circuitson the chip overall.

State of the art is that the instances of the circuits or books placedon a chip are fully designed and have static pin locations. Tointerconnect the corresponding pins, a wiring tool or a circuit designermanually retrieves the pin locations and routes the wires according tofree wiring channels. If a conflict-free wiring within one wiring levelis not possible, the wiring tool changes the wiring layer by using viasto connect all corresponding pins. Vias are small vertical connectorsbetween wiring layers and thus critical I manufacturing. Each via needsto have a certain distance to the next via which is higher than therequired distance between two wires. As vias are one of the main yieldlimiting factors of a design, it is often mandatory to add redundantvias to increase the overall yield. In these cases the via spacing rulebecomes more important and more chip area is needed to allow the wiring.In a full custom design it is also possible to duplicate the book undera different name and modify the pin locations in the copy manually.

U.S. Pat. No. 6,440,707 describes an automated method for routing anddesigning an LSI in which, first, an initial routing is performed on anet. If a design rule error exists in a wire already routed as a resultof initial routing, said wire is removed. Next, the terminals of theremoved wire are examined whether they are movable, which means freelyplaceable within a predetermined region of the design of the instancesto be connected. If at least one of said terminals is movable, it isdisplaced within the predetermined region and the removed wire isre-routed such that the displaced movable terminal is interconnected tothe other terminal. Thus, the movable terminal can be located at anappropriate position within the predetermined region in accordance withthe situation of surrounding wires.

The routing method disclosed in U.S. Pat. No. 6,440,707 is based onfully designed instances of books to be routed. A “book” is hereindefined as a switching element (transistor etc) or a logical unit (gate,latch like XOR or NAND gates) based on which a circuit design can begenerated. A designed circuit insofar represents a library consisting ofa multitude of books. The pin locations are either static, which meansfixed, or movable which means the pin location can vary as long as it isplaced within a defined region of the fully designed instance. Forinitial routing the movable pin locations are set according to designrules which have to consider the given layout of the instances. Only ifa design rule error occurs after initial routing the possibility ofdisplacing the already existing pins will be considered.

OBJECT OF THE INVENTION

Starting from this, the object of the present invention is to provide anautomated method for routing and designing an LSI which allows a furtherincrease of the wiring density and thus a further increase of thedensity of the circuits on the chip overall. Besides, the presentinvention provides a wiring tool and a layout generator which areespecially designed to carry out the method according to the presentinvention.

BRIEF SUMMARY OF THE INVENTION

The foregoing objects are achieved by a method and a wiring tool and alayout generator as laid out in the independent claims. Furtheradvantageous embodiments of the present invention are described in thesubclaims and are taught in the following description.

According to the present invention a method is provided for routing anddesigning an LSI (Large Scale Integrated Circuit), which uses so calledgenerics of the instances of books to be located and connected on thechip. A generic of an instance represents an area defined according tothe measurements of said instance. First, generics of the instances tobe connected are located on the chip. Then, an initial route betweensaid instances is generated by optimizing the route between thecorresponding generics according to given design rules. Thereby, it ispossible to determine optimized pin locations for said instances. Onlythen, by considering said optimized pin locations, a layout for each ofsaid instances is generated in place of the corresponding generics.Finally, the actually generated pins are connected with thecorresponding ends of the initial route.

This approach of routing and designing an LSI is based on the idea of anautomatic interaction between the wiring tool and a generator. Thelayout generator creates a layout for an instance based on parametersobtained by the wiring tool especially for the individual wiringsituation of said instance. Thus, multiple instances of the same bookcan have different parameter settings, especially different pinlocations, and different layout appearances.

As a consequence in a custom design environment, there is no need tocopy and modify the original book if a different pin location is desiredfor another instance of a book. Also, it is not necessary to maintainmultiple copies of the same book with only minor differences. As onlyone book needs to be designed and maintained, the design time can bereduced as well as the data volume of the design data.

In an ASIC design environment where it is not possible to copy andmanually modify the common books, the method proposed by the inventionsimplifies the wiring situation and therefore reduces the complexity ofthe wiring needed in several different aspects. One aspect is that themethod according to the present invention uses less wiring tracks tomake all necessary connections. Besides, if pins can be switched perinstance, potentially more wires can be routed straight to their pins.Another aspect is that the number of required wiring layers is reducedand therefore the number of vias, which imply via spacing design rules.Each of these aspects contributes to an increase of wiring density andthus of the density of the circuits on the chip overall.

The integration of more circuits on the same chip size will lead to ahigher functionality of the chips, on the one hand. On the other hand,an increase of chip density may reducer the chip size which impliesreduced manufacturing costs due to higher yield since there is aconstant number of defects per wafer area. Also, a reduced number ofvias on the chip will lead to a higher yield, as vias are one of themain yield limiting factors of a design.

A mixed design environment with custom and ASIC elements combines theadvantages mentioned above.

As mentioned above the initial route between two instances is generatedby considering given design rules. In an advantageous embodiment of thepresent invention the following design rules are considered:

-   -   minimum/maximum width and spacing of wires;    -   the length of the initial route should be as short as possible,    -   the position of the initial route should be available in one        layer,    -   the initial route is positioned in a predetermined layer. In        this context it should be mentioned that it is also possible to        consider less, more or different design rules by generating an        initial route without leaving the scope of protection of the        claimed invention.

The particular steps of the automatic method for routing and designingan LSI proposed by the present invention can be carried out by differenttools of a computer system. In an advantageous embodiment of the presentinvention a wiring tool generates the initial route, determines theoptimized pin location of an instance and passes the coordinates of saidoptimized pin location to a layout generator. Then this layout generatorcan create the layout of said instance by considering the optimized pinlocation determined by the wiring tool.

The connection between the actually generated pins of the instances andthe corresponding ends of the initial route can be generated by thelayout generator. In this case the layout generator has to create alayout for the area of the instances and besides a layout for a framearea surrounding the area of the instances and touching or including thecorresponding ends of the initial route. Here, the layout generator usesthe information about the optimized pin locations received from thewiring tool once for creating a layout of the instances and again forthe final routing of the actually generated pins.

In another embodiment of the present invention the wiring tool connectsthe actually generated pins with the corresponding ends of the initialroute. Therefore, the layout generator has to pass the coordinates ofthe actually generated pins to the wiring tool. Only then, the wiringtool is able to generate the connections necessary.

BRIEF DESCRIPTION OF THE DRAWINGS

The above, as well as additional objectives, features and advantages ofthe present invention, will be apparent in the following detaileddescription of an illustrative embodiment when read in conjunction withthe accompanying drawings, wherein:

FIG. 1 a shows a flow chart illustrating the particular steps of anautomated method for routing and designing an LSI according to thepresent invention;

FIG. 1 b shows two instances of books to be routed and designed atconsecutive states of processing which correspond to the stepsillustrated in FIG. 1 a.

DETAILED DESCRIPTION OF THE INVENTION

In the hereinafter described example the processing of an LSI startswith the location of the instances of books to be connected. As theseinstances are not yet fully designed they are called generics in termsof the present invention. A generic of an instance represents an area onthe chip where this instance shall be created during processing.Therefore, the area of a generic is defined according to themeasurements of the corresponding instance. In step 1 of the flow chartof FIG. 1 a the generics of two instances 10 and 11 are located on thechip. The connection between these instances 10 and 11 is not yetrouted.

In the next step 2 an initial route 12 is generated between saidinstances 10 and 11 by a wiring tool. Therefore, the route between thecorresponding generics is optimized according to the following designrules. The minimum/maximum width and spacing of wires has to beconsidered. The length of the initial route should be as short aspossible. Besides, the position of the initial route should be availablein one, here predetermined layer. The layer for wiring can be determinede.g. to optimize the performance of the net generated. As in this layera blockage 13 is located between the instances 10 and 11, a straightconnection between the instances 10 and 11 is not possible. Thus, theinitial route 12 detours the blockade 13.

On the base of the position and layout of the generated initial route 12it is now possible to determine an optimized pin location for each ofthe instances 10 and 11. In step 3 the coordinates of these optimizedpin locations are passed to a layout generator together with a requestfor corresponding pin locations to the instances. This is indicated bythe arrows 14 in FIG. 1 b.

Then, the layout generator creates the layout for each of the instances10 and 11 in place of the corresponding generics by considering thecorresponding optimized pin location. In case of instance 10, the pin 15could be created at the desired location. In case of instance 11, thedesired pin location was not available. Pin 16 had to be created alittle bit displaced to this desired location. The rest of the layout ofthe instances 10 and 11 is created and aligned as is state of the art.

In step 4 the layout generator returns the actual pin locations thatwere available to the wiring tool, what is indicated by the arrows 17.

In step 5 the wiring tool does the final route 18 to the actual pinlocations which means connecting the actually generated pins 15 and 16with the corresponding ends of the initial route 12.

As the actual wiring length can easily be determined by the wiring toolused according to the present invention the driver of the so generatednet can automatically be adapted to the chosen wiring solution.

As described above, the idea of the invention is that pin locations aredynamic and can be set according to the placement and wiring situation.This can be achieved by layout generators that can handle a set ofparameters and create a layout on the fly.

1. A layout generator for creating a layout of the instances of thebooks of an LSI, comprising: a layout generator which passes thecoordinates of a generated pin to a wiring tool and wherein said wiringtool connects the generated pin with the corresponding end of saidinitial route, and means for generating a layout for instances to beconnected of a circuit design book providing LSI switching elements andlogic units based on which a circuit design can be generated byconsidering predefined pin locations, especially pin locationsdetermined by said wiring tool.
 2. The layout generator according toclaim 1 further including means for generating an initial route betweentwo areas defined according to measurements of the size of said twoareas of said two instances to be connected, wherein the initial routeis optimized according to given design rules; and means for determiningan optimized pin location for said instances.